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1/20 n low power consumption: 230mw@40msps n single supply voltage: 2.5v independent supply for cmos output stage with 2.5v/3.3v capability n sfdr= -68.3 dbc @ fin=10mhz n 1ghz analog bandwidth track-and-hold n common clocking between channels n dual simultaneous sample and hold inputs n multiplexed outputs n built-in reference voltage with external bias capability description the tsa1203 is a new generation of high speed, dual-channel analog to digital converter pro- cessed in a mainstream 0.25m cmos technolo- gy yielding high performances and very low power consumption. the tsa1203 is specifically designed for applica- tions requiring very low noise floor, high sfdr and good isolation between channels. it is based on a pipeline structure and digital error correction to provide high static linearity at fs=40msps, and fin=10mhz. for each channel, a voltage reference is integrat- ed to simplify the design and minimize external components. it is nevertheless possible to use the circuit with external references. each adc outputs are multiplexed in a common bus with small number of pins. a tri-state capabili- ty is available for the outputs, allowing chip selec- tion. the inputs of the adc must be differentially driven. the tsa1203 is available in extended (0 to +85c) temperature range, in a small 48 pins tqfp package. applications n medical imaging and ultrasound n 3g basestation n i/q signal processing applications n high speed data acquisition system n portable instrumentation order code pin connections (top view) block diagram package part number temperature range package conditioning marking TSA1203IF 0c to +85c tqfp48 tray sa1203i TSA1203IFt 0c to +85c tqfp48 tape & reel sa1203i eval1203/ba evaluation board d0(lsb) gndbe d5 d6 d7 d8 d9 d10 d11(msb) avccb index corner 1 2 3 4 5 6 7 8 9 10 11 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 47 25 33 12 23 24 35 34 36 48 44 43 42 41 40 39 38 37 46 45 tsa1203 vccbe gndbe agnd ini agnd agnd ipol agnd agnd inbq inib agnd inq d2 d3 refmi oeb avcc refpi incmi avcc vccbi vccbi d1 vccbe select clk dgnd refpq agnd avcc dgnd dvcc dvcc incmq refmq gndbi d4 timing buffers ipol clk +2.5v/3.3v vini vinbi oeb vincmi gnd vinq vinbq vincmq ad 12 i channel ad 12 q channel 12 12 12 12 m u x ref i ref q select vrefpi vrefpq polar. vrefmi vrefmq common mode common mode d0 to d11 vccbe gndbe 7 7 mm tqfp48 tsa1203 dual-channel, 12-bit, 40msps, 230mw a/d converter february 2003
tsa1203 2/20 conditions avcc = dvcc = vccb = 2.5v, fs= 40msps, fin=10.13mhz, vin@ -1dbfs, vrefp=0.8v, vrefm=0v tamb = 25c (unless otherwise specified) dynamic characteristics timing characteristics symbol parameter test conditions min typ max unit sfdr spurious free dynamic range -68.3 -59.5 dbc snr signal to noise ratio 60.7 66.1 db thd total harmonics distortion -66.6 -58 dbc sinad signal to noise and distortion ratio 56.5 62.8 db enob effective number of bits 9.1 10.3 bits symbol parameter test conditions min typ max unit fs sampling frequency 0.5 40 mhz dc clock duty cycle 45 50 55 % tc1 clock pulse width (high) 22.5 25 ns tc2 clock pulse width (low) 22.5 25 ns tod data output delay (clock edge to data valid) 10pf load capacitance 9 ns tpd i data pipeline delay for i channel 7 cycles tpd q data pipeline delay for q channel 7.5 cycles ton falling edge of oeb to digital output valid data 1 ns toff rising edge of oeb to digital output tri-state 1 ns
tsa1203 3/20 timing diagram pin connections (top view) n-1 n n+1 n+6 n+7 n+2 n+5 n+3 n+4 n+8 clk tpd i + tod n+9 n+10 n+11 n+12 n+13 data output sample n+1 i channel sample n q channel sample n+1 q channel sample n+2 i channel sample n+2 q channel sample n+3 i channel oeb simultaneous sampling on i/q channels select sample n-9 i channel sample n-8 i channel sample n-7 q channel sample n-6 q channel clock and select connected together tod i q d0(lsb) gndbe d5 d6 d7 d8 d9 d10 d11(msb) avccb index corner 1 2 3 4 5 6 7 8 9 10 11 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 47 25 33 12 23 24 35 34 36 48 44 43 42 41 40 39 38 37 46 45 tsa1203 vccbe gndbe agnd ini agnd agnd ipol agnd agnd inbq inib agnd inq d2 d3 refmi oeb avcc refpi incmi avcc vccbi vccbi d1 vccbe select clk dgnd refpq agnd avcc dgnd dvcc dvcc incmq refmq gndbi d4
tsa1203 4/20 pin description electrical characteristics absolute maximum ratings pin no name description observation pin no name description observation 1 agnd analog ground 0v 25 gndbe digital buffer ground 0v 2 ini i channel analog input 26 vccbe digital buffer power supply 2.5v/3.3v 3 agnd analog ground 0v 27 d11(msb) most significant bit output cmos output (2.5v/3.3v) 4 inbi i channel inverted analog input 28 d10 digital output cmos output (2.5v/3.3v) 5 agnd analog ground 0v 29 d9 digital output cmos output (2.5v/3.3v) 6 ipol analog bias current input 30 d8 digital output cmos output (2.5v/3.3v) 7 avcc analog power supply 2.5v 31 d7 digital output cmos output (2.5v/3.3v) 8 agnd analog ground 0v 32 d6 digital output cmos output (2.5v/3.3v) 9 inq q channel analog input 33 d5 digital output cmos output (2.5v/3.3v) 10 agnd analog ground 0v 34 d4 digital output cmos output (2.5v/3.3v) 11 inbq q channel inverted analog input 35 d3 digital output cmos output (2.5v/3.3v) 12 agnd analog ground 0v 36 d2 digital output cmos output (2.5v/3.3v) 13 refpq q channel top reference voltage 37 d1 digital output cmos output (2.5v/3.3v) 14 refmq q channel bottom reference voltage 0v 38 d0(lsb) least significant bit output cmos output (2.5v/3.3v) 15 incmq q channel input common mode 39 vccbe digital buffer power supply 2.5v/3.3v - see application note 16 agnd analog ground 0v 40 gndbe digital buffer ground 0v 17 avcc analog power supply 2.5v 41 vccbi digital buffer power supply 2.5v 18 dvcc digital power supply 2.5v 42 vccbi digital buffer power supply 2.5v 19 dgnd digital ground 0v 43 oeb output enable input 2.5v/3.3v cmos input 20 clk clock input 2.5v cmos input 44 avcc analog power supply 2.5v 21 select channel selection 2.5v cmos input 45 avcc analog power supply 2.5v 22 dgnd digital ground 0v 46 incmi i channel input common mode 23 dvcc digital power supply 2.5v 47 refmi i channel bottom reference voltage 0v 24 gndbi digital buffer ground 0v 48 refpi i channel top reference voltage symbol parameter values unit avcc analog supply voltage 1) 1). all voltages values, except differential voltage, are with respect to network ground terminal. the magnitude of input and ou tput voltages must not exceed -0.3v or vcc 0 to 3.3 v dvcc digital supply voltage 1) 0 to 3.3 v vccbe digital buffer supply voltage 1) 0 to 3.6 v vccbi digital buffer supply voltage 1) 0 to 3.3 v idout digital output current -100 to 100 ma tstg storage temperature +150 c esd hbm: human body model 2) cdm: charged device model 3) 2). electrostatic discharge pulse (esd pulse) simulating a human body discharge of 100 pf through 1.5k w 3). discharge to ground of a device that has been previously charged. 2 1.5 kv latch-up class 4) 4). corporate st microelectronics procedure number 0018695 a
tsa1203 5/20 operating conditions analog inputs digital inputs and outputs symbol parameter min typ max unit avcc analog supply voltage 2.25 2.5 2.7 v dvcc digital supply voltage 2.25 2.5 2.7 v vccbe external digital buffer supply voltage 2.25 2.5 3.5 v vccbi internal digital buffer supply voltage 2.25 2.5 2.7 v vrefpi vrefpq forced top voltage reference 0.94 1.4 v vrefmi vrefmq forced bottom reference voltage 0 0.4 v incmi incmq forced input common mode voltage 0.2 1 v symbol parameter test conditions min typ max unit vin-vinb full scale reference voltage differential inputs mandatory 1.1 2.0 2.8 vpp cin input capacitance 7.0 pf req equivalent input resistor 10 k w bw analog input bandwidth vin@full scale, fs=40msps 1000 mhz erb effective resolution bandwidth 70 mhz symbol parameter test conditions min typ max unit clock and select inputs vil logic "0" voltage 0 0.8 v vih logic "1" voltage 2.0 2.5 v oeb input vil logic "0" voltage 0 0.25 x vccbe v vih logic "1" voltage 0.75 x vccbe vccbe v digital outputs vol logic "0" voltage iol=10a 0 0.1 x vccbe v voh logic "1" voltage ioh=10a 0.9 x vccbe vccbe v ioz high impedance leakage current oeb set to vih -1.67 0 1.67 a c l output load capacitance 15 pf
tsa1203 6/20 conditions avcc = dvcc = vccb = 2.5v, fs= 40msps, fin=2mhz, vin@ -1dbfs, vrefp=0.8v, vrefm=0v tamb = 25c (unless otherwise specified) reference voltage power consumption accuracy matching between channels symbol parameter test conditions min typ max unit vrefpi vrefpq top internal reference voltage 0.81 0.88 0.94 v vincmi vincmq input common mode voltage 0.41 0.46 0.50 v symbol parameter min typ max unit icca analog supply current 82 96.5 ma iccd digital supply current 4.4 4.9 ma iccbe digital buffer supply current (10pf load) 6.6 9.4 ma iccbi digital buffer supply current 274 440 m a pd power consumption in normal operation mode 230 271 mw rthja thermal resistance (tqfp48) 80 c/w symbol parameter min typ max unit oe offset error 2.97 lsb ge gain error 0.1 % dnl differential non linearity 0.52 lsb inl integral non linearity 3 lsb - monotonicity and no missing codes guaranteed symbol parameter min typ max unit gm gain match 0.04 1 % om offset match 0.88 lsb phm phase match 1 dg xtlk crosstalk rejection 85 db
tsa1203 7/20 definitions of specified parameters static parameters static measurements are performed through method of histograms on a 2mhz input signal, sampled at 40msps, which is high enough to fully characterize the test frequency response. the input level is +1dbfs to saturate the signal. differential non linearity (dnl) the average deviation of any output code width from the ideal code width of 1 lsb. integral non linearity (inl) an ideal converter presents a transfer function as being the straight line from the starting code to the ending code. the inl is the deviation for each transition from this ideal curve. dynamic parameters dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 40msps. the input level is -1dbfs to measure the linear behavior of the converter. all the parameters are given without correction for the full scale ampli- tude performance except the calculated enob parameter. spurious free dynamic range (sfdr) the ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full nyquist band. it is expressed in dbc. total harmonic distortion (thd) the ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. it is expressed in db. signal to noise ratio (snr) the ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the nyquist band (f s /2) excluding dc, fundamental and the first five harmonics. snr is reported in db. signal to noise and distortion ratio (sinad) similar ratio as for snr but including the harmonic distortion components in the noise figure (not dc signal). it is expressed in db. from the sinad, the effective number of bits (enob) can easily be deduced using the formula: sinad= 6.02 enob + 1.76 db. when the applied signal is not full scale (fs), but has an a 0 amplitude, the sinad expression becomes: sinad 2ao =sinad full scale + 20 log (2a 0 /fs) sinad 2ao =6.02 enob + 1.76 db + 20 log (2a 0 / fs) the enob is expressed in bits. analog input bandwidth the maximum analog input frequency at which the spectral response of a full power signal is reduced by 3db. higher values can be achieved with smaller input levels. effective resolution bandwidth (erb) the band of input signal frequencies that the adc is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the sinad is decreased by 3db or the enob by 1/2 bit. pipeline delay delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. also called data latency. it is expressed as a number of clock cycles.
tsa1203 8/20 static parameter: integral non linearity fs=40msps; icca=60ma; fin=2mhz static parameter: differential non linearity fs=40msps; icca=60ma; fin=2mhz linearity vs. fs fin=5mhz distortion vs. fs fin=5mhz -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 500 1000 1500 2000 2500 3000 3500 4000 output code inl (lsbs) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0 500 1000 1500 2000 2500 3000 3500 4000 output code dnl (lsbs) 55 60 65 70 75 80 35 40 45 50 fs (mhz) dynamic parameters (db) 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 enob (bits) enob_i sinad_i enob_q snr_q sinad_q snr_i -100 -90 -80 -70 -60 -50 -40 35 40 45 50 fs (mhz) dynamic parameters (dbc) thd_i sfdr_i thd_q sfdr_q
tsa1203 9/20 linearity vs. fin fs=40mhz; icca=60ma linearity vs. temperature fs=40mhz; icca=60ma; fin=2mhz linearity vs. avcc fs=40msps; icca=60ma; fin=10mhz distortion vs. fin fs=40mhz; icca=60ma distortion vs.temperature fs=40msps; icca=60ma; fin=2mhz distortion vs. avcc fs=40msps; icca=60ma; fin=10mhz 50 55 60 65 70 75 80 85 90 0 20406080 fin (mhz) dynamic parameters (db) 6 7 8 9 10 11 12 enob (bits) enob_q sinad_q sinad_i snr_q snr_i enob_i 50 55 60 65 70 75 80 85 90 -40 10 60 110 temperature (c) dynamic parameters (db) 4 5 6 7 8 9 10 11 12 enob (bits) sinad_q snr_q enob_q enob_i snr_i sinad_i 50 52 54 56 58 60 62 64 66 68 70 2.25 2.35 2.45 2.55 2.65 avcc (v) dynamic parameters (db) 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q -100 -90 -80 -70 -60 -50 -40 0 20406080 fin (mhz) dynamic parameters (dbc) sfdr_i sfdr_q thd_i thd_q 50 55 60 65 70 75 80 85 90 95 100 -40 10 60 110 temperature (c) dynamic parameters (dbc) thd_q sfdr_q thd_i sfdr_i -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 2.25 2.35 2.45 2.55 2.65 avcc (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i
tsa1203 10/20 linearity vs. dvcc fs=40msps; icca=60ma; fin=10mhz linearity vs. vccbi fs=40msps; icca=60ma; fin=10mhz linearity vs. vccbe fs=40msps; icca=60ma; fin=5mhz distortion vs. dvcc fs=40msps; icca=60ma; fin=10mhz distortion vs. vccbi fs=40msps; icca=60ma; fin=10mhz distortion vs. vccbe fs=40msps; icca=60ma; fin=5mhz 50 52 54 56 58 60 62 64 66 68 70 2.25 2.35 2.45 2.55 2.65 dvcc (v) dynamic parameters (db) 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q 50 52 54 56 58 60 62 64 66 68 70 2.25 2.35 2.45 2.55 2.65 vccbi (v) dynamic parameters (db) 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q 60 61 62 63 64 65 66 67 68 69 70 2.25 2.75 3.25 vccbe (v) dynamic parameters (db) 8 8.5 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q -90 -85 -80 -75 -70 -65 -60 -55 -50 2.25 2.35 2.45 2.55 2.65 dvcc (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i -90 -85 -80 -75 -70 -65 -60 -55 -50 2.25 2.35 2.45 2.55 2.65 vccbi (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i -110 -100 -90 -80 -70 -60 -50 -40 2.25 2.75 3.25 vccbe (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i
tsa1203 11/20 linearity vs. duty cycle fs=40mhz; icca=60ma; fin=5mhz distortion vs. duty cycle fs=40mhz; icca=60ma; fin=5mhz single-tone 8k fft at 40msps - q channel fin=5mhz; icca=60ma, vin@-1dbfs dual-tone 8k fft at 40msps - q channel fin1=0.93mhz; fin2=1.11mhz; icca=70ma, vin1@-7dbfs; vin2@-7dbfs; imd=-69dbc 40 50 60 70 80 90 100 48 49 50 51 52 positive duty cycle (%) dynamic parameters (db) 4 5 6 7 8 9 10 11 12 enob (bits) sinad_q snr_q enob_q enob_i snr_i sinad_i -100 -90 -80 -70 -60 -50 -40 48 49 50 51 52 positive duty cycle (%) dynamic parameters (dbc) thd_q sfdr_q thd_i sfdr_i 2 4 6 8 1214161820 10 -20 -40 -60 -100 -80 -140 0 -120 frequency (mhz) power spectrum (db) 2.5 5 7.5 10 15 17.5 20 12.5 -20 -40 -60 -100 -80 0 -120 frequency (mhz) power spectrum (db)
12/20 tsa1203 application note detailed information the tsa1203 is a dual-channel, 12-bit resolution high speed analog to digital converter based on a pipeline structure and the latest deep sub micron cmos process to achieve the best performances in terms of linearity and power consumption. each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. a latency time of 7 clock periods is necessary to ob- tain the digitized data on the output bus. the input signals are simultaneously sampled on both channels on the rising edge of the clock. the output data are valid on the rising edge of the clock for i channel and on the falling edge of the clock for q channel. the digital data out from the different stages must be time delayed depending on their order of conversion. then a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. the structure has been specifically designed to accept differential signals. the tsa1203 is pin to pin compatible with the dual 10 bits/20msps, tsa1005-20, the dual 10bits /40msps, tsa1005-40 and the dual 12bits/ 20msps,tsa1204. complementary functions some functionalities have been added in order to simplify as much as possible the application board. these operational modes are described as followed. output enable (oeb) when set to low level (vil), all digital outputs remain active and are in low impedance state. when set to high level (vih), all digital outputs buffers are in high impedance state while the converter goes on sampling. when oeb is set to a low level again, the data are then present on the output with a very short ton delay. therefore, this allows the chip select of the device. the timing diagram summarizes this functionality. in order to remain in the normal operating mode, this pin should be grounded through a low value of resistor. select the digital data out from each adc cores are mul- tiplexed together to share the same output bus. this prevents from increasing the number of pins and enables to keep the same package as single channel adc like tsa1201. the selection of the channel information is done through the "select" pin. when set to high level (vih), the i channel data are present on the bus d0-d11. when set to low level (vil), the q chan- nel data are on the output bus d0-d11. connecting select to clk allows i and q chan- nels to be simultaneously present on d0-d11; i channel on the rising edge of the clock and q channel on the falling edge of the clock. (see tim- ing diagram page 2). references and common mode connection vrefm must be always connected externally. internal reference and common mode in the default configuration, the adc operates with its own reference and common mode voltages generated by its internal bandgap. vrefm pins are connected externally to the analog ground while vrefp (respectively incm) are set to their internal voltage of 0.89v (respectively 0.46v). it is recommended to decouple the vrefp and incm in order to minimize low and high frequency noise (refer to figure 1). figure 1 : internal reference and common mode setting tsa1203 vin vinb vrefm 1.03v vrefp 330pf 4.7uf 10nf incm 330pf 4.7uf 10nf 0.57v
tsa1203 13/20 external reference and common mode each of the voltages vrefp and incm can be fixed externally to better fit to the application needs (refer to table operating conditions page 5 for min/max values). the vrefp, vrefm voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(vrefp-vrefm). using internal references, the dynamic range is 1.8v. the best linearity and distortion performances are achieved with a dynamic range above 2vpp and by increasing the vrefm voltage instead of lowering the vrefp one. the incm is the mid voltage of the analog input signal. it is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. using the stmicroelectronics ts821 or ts4041-1.2 vref leads to optimum performances when configured as shown on figure 2. figure 2 : external reference setting driving the differential analog inputs the tsa1203 has been designed to obtain optimum performances when being differentially driven. an rf transformer is a good way to achieve such performances. figure 3 describes the schematics. the input signal is fed to the primary of the transformer, while the secondary drives both adc inputs. the common mode voltage of the adc (incm) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46v. it determines the dc component of the analog signal. as being an high impedance input, it acts as an i/o and can be externally driven to adjust this dc component. the incm is decoupled to maintain a low noise level on this node. our evaluation board is mounted with a 1:1 adt1-1wt transformer from minicircuits. you might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. each analog input can drive a 1.4vpp amplitude input signal, so the resultant differential amplitude is 2.8vpp. figure 3 : differential input configuration with transformer figure 4 represents the biasing of a differential input signal in ac-coupled differential input configuration. both inputs vin and vinb are centered around the common mode voltage, that can be let internal or fixed externally. figure 4 : ac-coupled differential input figure 5 shows a dc-coupled configuration with forced vrefp and incm to the 1v dc analog input while vrefm is connected to ground; we achieve a 2vpp differential amplitude. 1k w tsa1203 vin vinb vrefm vrefp external reference vcca 330pf 4.7uf 10nf ts821 ts4041 tsa1203 vin vinb incm 50 w 33pf 330pf 470nf 10nf analog source 1:1 adt1-1 i or q ch. 50 w 10nf tsa1203 vin vinb incm 33pf 100k w 100k w 50 w 10nf common mode
tsa1203 14/20 figure 5 : dc-coupled 2vpp differential analog input clock input the tsa1203 performance is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. the duty cycle must be between 45% and 55%. the clock power supplies must be separated from the adc output ones to avoid digital noise modulation at the output. it is recommended to keep the circuit clocked, to avoid random states, before applying the supply voltages. power consumption so as to optimize both performance and power consumption of the tsa1203 according the sampling frequency, a resistor is placed between ipol and the analog ground pins. therefore, the total dissipation is adjustable from 30msps up to 40msps. the tsa1203 will combine highest performances and lowest consumption at 40msps when rpol is equal to 18k w . this value is nevertheless depen- dant on application and environment. at lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. the table below sums up the relevant data. figure 6 : total power consumption optimization depending on rpol value application layout precautions to use the adc circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - first of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the pcb is advised for high speed circuit applications to provide low inductance and low resistance common return. the separation of the analog signal from the digital part is mandatory to prevent noise from coupling onto the input signal. the best compromise is to connect from one part agnd, dgnd, gndbi in a common point whereas gndbe must be isolated. similarly, the power supplies avcc, dvcc and vccbi must be separated from the vccbe one. - power supply bypass capacitors must be placed as close as possible to the ic pins in order to improve high frequency bypassing and reduce harmonic distortion. - proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. all leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - to keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. to minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - choose component sizes as small as possible (smd). digital interface application thanks to its wide external buffer power supply range, the tsa1203 is perfectly suitable to plug in to 2.5v low voltage dsps or digital interfaces as well as to 3.3v ones. medical imaging application driven by the demand of the applications requiring nowadays either portability or high degree of par- allelism (or both), this product has been devel- oped to satisfy medical imaging, and telecom in- frastructures needs. as a typical system diagram shows figure 7, a nar- row input beam of acoustic energy is sent into a living body via the transducer and the energy re- flected back is analyzed. fs (msps) 30 35 40 rpol ( k w) 38 28 18 optimized power (mw) 145 180 230 tsa1203 vin vinb incm 330pf 4.7uf 10nf analog dc ac+dc vrefp vrefm vrefp-vrefm = 1 v dc analog
tsa1203 15/20 figure 7 : medical imaging application the transducer is a piezoelectric ceramic such as zirconium titanate. the whole array can reach up to 512 channels. the tx beam former, amplified by the hv tx amps, delivers up to 100v amplitude excitation pulses with phase and amplitude shifts. the mux and t/r switch is a two way input signal transmitter/ output receiver. to compensate for skin and tissues attenuation effects, the time gain compensation (tgc) am- plifier is an exponential amplifier that enables the amplification of low voltage signals to the adc in- put range. differential output structure with low noise and very high linearity are mandatory fac- tors. these applications need high speed, low power and high performance adcs. 10-12 bit resolution is necessary to lower the quantification noise. as multiple channels are used, a dual con- verter is a must for room saving issues. the input signal is in the range of 2 to 20mhz (mainly 2 to 7mhz) and the application uses most- ly a 4 over-sampling ratio for spurious free dy- namic range (sfdr) optimization. the next rx beam former and processing blocks enable the analysis of the outputs channels ver- sus the input beam. eval1203/ba evaluation board the eval1203/ba is a 4-layer board with high decoupling and grounding level. the schematic of the evaluation board is reported figure 11 and its top overlay view figure 10. the characterization of the board has been made with a fully adc devoted test bench as shown on figure 8. the analog input signal must be filtered to be very pure. the dataready signal is the acquisition clock of the logic analyzer. the adc digital outputs are latched by the octal buffers 74lcx573. all characterization measurements have been made with: - sfsr=1db for static parameters. - sfsr=-1db for dynamic parameters. figure 8 : analog to digital converter characterization bench mux and t/r switches tx beam former processing and display rx beam former adc tgc amplifier hv tx amps sine wave generator hp8644 adc evaluation board pulse generator logic analyzer sine wave generator hp8644 hp8133 vin clk data clk pc
tsa1203 16/20 operating conditions of the evaluation board: find below the connections to the board for the power supplies and other pins: care should be taken for the evaluation board considering the fact that the outputs of the con- verter are 2.5v/3.3v (vccb2) tolerant whereas the 74lcx573 external buffers are operating up to 2.5v. single and differential inputs: the adc board components are mounted to test the tsa1203 with single analog input; the adt1-1wt transformer enables the differential drive into the converter; in this configuration, the resistors rsi6, rsi7, rsi8 for i channel (respec- tively rsq6, rsq7, rsq8 for q one) are con- nected as short circuits whereas rsi5, rsi9 (re- spectively rsq5, rsq9) are open circuits. the other way is to test it via ji1 and ji1b differen- tial inputs. so, the resistances rsi5, rsi9 for i channel (respectively rsq5, rsq9 for q one) are connected as short circuits whereas rsi6, rsi7, rsi8 (respectively rsq6, rsq7, rsq8 for q one) are open circuits. grounding consideration so as to better reject noise on the board, connect on the bottom overlay ag (agnd), dg(dgnd), gb1(gndbi) together from one part, and gb2(gndbe) with gb3(gndb3) from the other part. mode select so as to evaluate a single channel or the dual ones, you have to connect on the board the relevant position for the select pin (see figure 9) with the strap connected - to the upper connectors, the i channel at the out- put is selected. - horizontally, the q channel at the output is se- lected. - to the lower connectors, both channels are se- lected, relative to the clock edge. figure 9 : mode select consumption adjustment before any characterization, care should be taken to adjust the rpol (raj1) and therefore ipol value in function of your sampling frequency. board notation connection internal voltage (v) external voltage (v) av av cc 2.5 ag agnd 0 rpi refpi 0.89 <1.4 rmi refmi <0.4 cmi incmi 0.46 <1 rpq refpq 0.89 <1.4 rmq refmq <0.4 cmq incmq 0.46 <1 dv dvcc 2.5 dg dgnd 0 gb1 gndbi 0 vb1 vccbi 2.5 gb2 gndbe 0 vb2 vccbe 2.5/3.3 gb3 gndb3 0 vb3 vccb3 2.5 select dvcc dgnd clk i channel q channel i/q channels select schematic board
tsa1203 17/20 figure 10 : printed circuit of evaluation board.
tsa1203 18/20 figure 11 : tsa1203 evaluation board schematic ri1 50 r2 1k r3 50 ci1 33pf c2 330pf c3 470nf c4 10nf ci8 330pf ci9 10nf ci10 470nf ci11 330pf ci12 10nf ci13 470nf c14 330pf c15 10nf c16 470nf raj1 47k c17 330pf c18 10nf c19 470nf j4 clk oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u2 74lcx573 oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u3 74lcx573 r11 47k c25 330pf c27 10nf c28 470nf + c29 10f do d7 d8 d9 d10 d11 ci30 330pf ci31 10nf ci32 470nf + c34 47f + c35 47f avcc vccb2 vccb1 c26 330pf c39 10nf c37 470nf vccb3 c33 330pf c40 10nf c38 470nf c41 10f + c42 47f clk d1 d2 d3 d4 d5 d6 c20 330pf c21 10nf c22 470nf c23 10f + c36 47f 1 4 3 2 6 ti2 t2-at1-1wt ji1b inib r5 50 j25 ckdata 1 2 j27 con2 ri19 50 s4 sw-spst vccb1 gndb 1 vccb 1 gndb 2 vccb 2 gndb 3 vccb 3 j17 bufpow d0 gnd d1 gnd d2 gnd d3 gnd d4 gnd d5 gnd d6 gnd d7 gnd d8 gnd d9 gnd d10 gnd d11 gnd clk gnd avcc c5 100nf ci6 nm vccb2 c51 330pf c52 10nf c53 470nf rsi5 0 nc rsi6 0 rsi7 0 rsi8 0 rsi9 0 nc nm: non soud analog input with transformer (default) rs5 rs6 rs7 rs8 rs9 c c c c c c c single input differential input 1 2 j26 con2 agnd 1 ini 2 agnd 3 inbi 4 agnd 5 ipol 6 avcc 7 agnd 8 inq 9 agnd 10 inbq 11 agnd 12 refpq 13 refmq 14 incmq 15 agnd 16 avcc 17 dvcc 18 dgnd 19 clk 20 select 21 dgnd 22 dvcc 23 gndbi 24 gndbe 25 vccbe 26 d11(msb) 27 d10 28 d9 29 d8 30 d7 31 d6 32 d5 33 d4 34 d3 35 d2 36 d1 37 d0(lsb) 38 vccbe 39 gndbe 40 vccbi 41 vccbi 42 oeb 43 avcc 44 avcc 45 incmi 46 refmi 47 refpi 48 8-14bits adc j9 adc dual12b cd3 330pf cd2 10nf cd1 470nf 1 q rq1 50 cq1 33pf cq8 330pf cq9 10nf cq10 470nf cq11 330pf cq12 10nf cq13 470nf cq30 330pf cq31 10nf cq32 470nf 1 4 3 2 6 tq2 t2-at1-1wt jq1b inqb rq19 50 cq6 nm rsq5 0 nc rsq6 0 rsq7 0 rsq8 0 rsq9 0 nc avcc c10 330pf c11 10nf c13 470nf c31 10f + c32 47f dvcc dvcc dvcc r21 0nm r22 0nm r23 0nm r24 0nm refp ref m incm ji2 vrefi refp refm incm jq2 vrefq gnd vcc ja analogi c g nd v cc jd digital vccb1 sw1 s5 sw-spst in vc c gnd s1 s2 d u1 stg719 vccb2 vccb2 r12 47k c43 10f + c44 47f vccb3 vccb2 switch s4 oeb mode open normal mode short high impedance output mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 j6 switch s5 open normal mode short test mode
tsa1203 19/20 figure 12 : printed circuit board - list of components name footprint name footprint name footprint name part footprint type rsq6 0 805 cd2 10nf 603 c26 330pf 603 cq6 nc 805 rsq7 0 805 c40 10nf 603 c20 330pf 603 ci6 nc 805 rsq8 0 805 c39 10nf 603 c33 330pf 603 u2 74lcx573 tssop20 rsi6 0 805 cq12 10nf 603 c25 330pf 603 u3 74lcx573 tssop20 rsi7 0 805 cq9 10nf 603 ci1 33pf 603 u1 stg719 sot23-6 rsi8 0 805 c52 10nf 603 cq1 33pf 603 ja analogic connector r3 47 603 c18 10nf 603 c34 47f rb.1 j17 bufpow connector r5 47 603 c21 10nf 603 c42 47f rb.1 j25 ckdata sma rq19 47 603 c4 10nf 603 c35 47f rb.1 j4 clk sma ri1 47 603 c15 10nf 603 c44 47f rb.1 j27 con2 sip2 rq1 47 603 c27 10nf 603 c36 47f rb.1 j26 con2 sip2 ri19 47 603 c11 10nf 603 c32 47f rb.1 jd digital connector rsi9 0nc 805 ci9 10nf 603 c37 470nf 805 ji1 ini sma rsq5 0nc 805 ci12 10nf 603 cq10 470nf 805 ji1b inib sma rsq9 0nc 805 ci31 10nf 603 c28 470nf 805 jq1 inq sma rsi5 0nc 805 cq31 10nf 603 ci10 470nf 805 jq1b inqb sma r24 0nc 805 cq30 330pf 603 cq32 470nf 805 sw1 switch connector r23 0nc 805 ci11 330pf 603 cq13 470nf 805 s5 sw-spst connector r21 0nc 805 c51 330pf 603 ci32 470nf 805 s4 sw-spst connector r22 0nc 805 c2 330pf 603 c13 470nf 805 ti2 t2-at1-1wt adt r2 1k 603 c17 330pf 603 c53 470nf 805 tq2 t2-at1-1wt adt r12 47k 603 cd3 330pf 603 c16 470nf 805 ji2 vrefi connector r11 47k 603 c10 330pf 603 c3 470nf 805 jq2 vrefq connector raj1 200k cq8 330pf 603 c22 470nf 805 j6 32pin cq11 330pf 603 ci13 470nf 805 c23 10f 1210 ci8 330pf 603 c38 470nf 805 c41 10f 1210 c14 330pf 603 cd1 470nf 805 nc: non soldered c29 10f 1210 ci30 330pf 603 c19 470nf 805 vr5 trimmer idc-32 connector part type part type part type
tsa1203 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom http://www.st.com package mechanical data 48 pins - plastic package dim. millimeters inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 d3 5.50 0.216 e 0.50 0.0197 e 9.00 0.354 e1 7.00 0.276 e3 5.50 0.216 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 7 (max.) 48 37 d3 e 13 24 1 12 25 36 c a1 a2 a d1 d e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane b

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